A dynamic frequency scaling (DFS) scheme based on resonant rotary clocking may address certain needs:
1) The power savings and the stability of the resonant rotary clocking are directly proportional to its operating frequency; thus, lower frequency implementations of rotary clocking are often inefficient. For instance, when the resonant clocking implementation on AMD Piledriver chip is used at high frequencies, and the clock network is multiplexed off to be driven by a non-resonant clock source for lower frequency modes.
2) While a frequency division circuitry exists for resonant rotary clocking (e.g. not for coupled LC oscillator-based type that is used but for RTWO), the rotary clock frequency divider is a static divider and cannot perform dynamic frequency scaling as targeted in this work for DFS-based architectural design support.
The second challenge listed above refers to prior work on resonant clock frequency division described in US publication 2008/0258780. This describes a circuitry for frequency division designed specifically for the RTWO-based resonant clocking that uses the SABs driven by multi-phases of the rotary clock. As described herein, an RTWO frequency divider design methodology is based on the SAB for dynamic frequency scaling. Using this methodology, an RTWO frequency divider for integer division ratios of 3 to 9 may be realized based on one circuit topology.